1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to semiconductor devices or integrated circuits with compliant interconnects.
2. Related Art
With the introduction of low-k and ultra-low-k dielectrics in semiconductor manufacture, the effect of packaging stresses on the semiconductor die has increased dramatically. These brittle dielectric materials are sensitive to stresses imposed by the packaging. A major challenge in the industry is die dielectric delamination below the flip chip interconnect between the die and the package substrate. Because of the visual signal this delamination creates in scanning acoustic microscopy, this defect is termed “white bump”. The stress contributing to “white bumps” originates from the difference in coefficients of thermal expansion between the silicon die and the package substrate, and the resulting deformation or bending of the interconnects during die attach solder reflow cooldown.
Currently, the interconnect can be a solder bump with thin Ni (less than or equal to 3 um) underbump metallurgy on the die side or a thick (greater than 20 um) Cu stud with a Sn-based solder cap. Both of these solutions are rigid enough to transfer a significant amount of stress to the die dielectric. The interconnect cross-sectional area must be large enough to provide acceptable life in spite of electromigration deterioration that occurs. This large area creates a rigid bump structure that is susceptible to packaging stresses.